This invention relates to acquisition of a direct-sequence, spread-spectrum signal, and more particularly to an improvement in apparatus and method using counters with a bank of product devices.
Code division multiple access (CDMA) or spread-spectrum receivers are made either using a single correlator, a matched filter, or a bank of correlators. A typical prior art approach, shown in FIG. 1, is to generate an in-phase component and a quadrature-phase component of a spread-spectrum signal, with in-phase mixer 17 and quadrature-phase mixer 18. The in-phase mixer 17 multiplies the spread-spectrum signal with a cosine signal at the spread-spectrum carrier frequency, cos(xcfx89ot), and the quadrature-phase mixer 18 multiplies the spread-spectrum signal with a sine signal at the spread-spectrum frequency, sin(xcfx89ot). The resulting in-phase component is despread by an in-phase despreader 19, and the resulting the quadrature-phase component is despread by a quadrature-phase despreader 20. Outputs from the in-phase despreader 19 and the quadrature-phase despreader 20 are combined by a combiner 15. The in-phase despreader 19 and the quadrature-phase despreader 20, may be embodied as a matched filter having an impulse response matched to the chip-sequence signal, a correlator, or a bank of correlators. While the matched filter, correlator or bank of correlators eventually result in a synchronized system, major differences exist between them.
The single correlator compares, cross-correlates, the incoming spread-spectrum signal to a stored reference signal. The stored reference signal typically is a replica or delayed replica of the chip-sequence signal which forms the spread-spectrum signal. If the cross-correlation were not acceptable, then the reference signal is delayed or advanced and the procedure for cross-correlating is repeated, until synchronization is achieved. This procedure is a time consuming process and disadvantageous when fast acquisition is required.
The matched filter often is referred to as a camp and wait technique. The incoming signal slides through the matched filter until the incoming signal matches the replica of the chip-sequence signal, or impulse response of the matched filter. An output then occurs. The matched filter suffers from the fact that the adders employed are required to operate at a speed which is a high multiple of the chip rate, which is a large number. The many required adders also consumes power. Hence, power consumption and high speed are limitations of the matched filter.
The bank of correlators is a group of correlators in which the stored reference of each correlator is delayed from the stored reference for other correlators, by a fraction of a chip, most typically xc2xd of one chip. The adder used in each correlator is updated only once each chip, but many adders are required, one for each correlator. Thus, while the synchronization time achievable is the same as for the matched filter, a fundamental limitation of the bank or correlators is the large number of adders required.
A general object of the invention is to achieve comparable performance of the matched filter or bank of correlators, with significantly lower complexity as found in the matched filter or bank of correlators.
Another object of the invention is lower power consumption and ability to operate at higher chip rates than the designs of current matched filters and bank of correlators.
According to the present invention, as embodied and broadly described herein, an improvement for acquiring synchronization to a chip-sequence signal is provided. The chip-sequence signal has a plurality of chips. The improvement comprises a shift register, a plurality of comparators, a plurality of counters, and a selector. A spread-spectrum signal, as used herein, typically includes a sequence of bits represented as a data signal, multiplied by a sequence of chips represented as a chip-sequence signal, raised to a carrier frequence by a carrier signal. For synchronization, the data signal typically is a constant value, for example, a series of one bits, or has very slowly time-varying data.
A local reference signal continually is cycled through the shift register. The local reference signal is a replica or delayed replica of the chip-sequence signal. The shift register has a plurality of taps, which correspond to the plurality of chips.
The plurality of comparators is connected to the plurality of taps, respectively. The plurality of comparators may be embodied as one or more AND gates, OR gates and/or NOR gates, or as a product device. The plurality of comparators compares the incoming chip-sequence signal with the replica of the chip-sequence signal stored in the shift register. From the comparison, the plurality of comparators generates, for each tap of the shift register, a plurality of compared values at each output of each comparator of the plurality of comparators. From a sequence of comparisons occurring in time, a multiplicity of compared values appears at the output of a specific comparator.
The plurality of counters is connected to the plurality of comparators. The plurality of counters are designed to count up and down. The respective multiplicity of compared values appears at an output of a respective comparator of the plurality of comparators. The plurality of counters thereby generates a plurality of totals, respectively. A particular total results from a particular counter, up and down counting a particular multiplicity of compared values at the output of a particular comparator.
The selector is coupled to the plurality of counters. The selector selects a value from the plurality of totals. The selected value may be, by way of example, a largest value, a maximum likely value, or a value which exceeds a threshold. If in-phase and quadrature phase components are used, then these components are combined prior to comparing to a threshold.
The present invention also includes a method for acquiring synchronization to a chip-sequence signal embedded in a spread-spectrum signal. The chip-sequence signal has a plurality of chips. The method comprises the steps of storing a replica or delayed replica of the chip-sequence signal in a device having a plurality of taps corresponding to the plurality of chips, respectively; comparing the chip-sequence signal embedded in the spread-spectrum signal with the replica of the chip-sequence signal present at the plurality of taps, thereby generating for each tap of the device a plurality of compared values, respectively; up and down counting, from each output of the device, a respective plurality of compared values, respectively, thereby generating a plurality of totals, respectively; and selecting a value from the plurality of totals.
The term xe2x80x9cprocessing bitxe2x80x9d, as encountered in soft decision, refers to the bit or bits, representing a chip in the shift register, and used thereafter for processing through the plurality of comparators and the plurality of counters. In a hard limiter, or hard decision, embodiment, there is one processing bit per sample of a chip. Thus, the compared value is represented as one processing bit, and the corresponding counter may count up or down by one bit. With soft decision, there are multiple processing bits per sample of a chip, and the compared vales are embodied as multiple processing bits. For example, for two processing bits, the counter counts up/down by one or two, and for three processing bits per chip sample, the counter counts up/down by one, two, three, or four or equivalently counts between one and eight. By having a preset counter, the counting process may be bypassed.
Additional objects and advantages of the invention are set forth in part in the description which follows, and in part are obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention also may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.